`timescale 1ns / 1ps
module test_xmj_ff;
	reg CLK1;
	wire CLK2;
	xmj_Fractional_Frequency uut (
		.CLK1(CLK1), 
		.CLK2(CLK2)
	);

	initial begin
		CLK1 = 0;
		forever begin
			#5 CLK1 = ~CLK1;
		end
	end
      
endmodule

